Please use this identifier to cite or link to this item:
http://cmuir.cmu.ac.th/jspui/handle/6653943832/78469
Title: | การลดข้อบกพร่องในการประกอบแผงวงจรพิมพ์โดยเทคนิคซิกซ์ซิกมา |
Other Titles: | Defect reduction in printed circuit board assembly by six sigma technique |
Authors: | ยุทธนา คำพูน |
Authors: | รุ่งฉัตร ชมภูอินไหว ยุทธนา คำพูน |
Issue Date: | Jun-2023 |
Publisher: | เชียงใหม่ : บัณฑิตวิทยาลัย มหาวิทยาลัยเชียงใหม่ |
Abstract: | The Case Study Company is engaged in the manufacturing and distribution of electronic products. It has identified the BA0028 circuit board as having the highest defect rate, approximately 40%. Therefore, the objective of this research is to Defect Reduction in Printed Circuit Board Assembly by Six Sigma Technique. A 5-step Six Sigma process DMAIC, which includes Define, Measure, Analyze, Improve, and Control. The production process of the product was thoroughly studied by creating a process flow diagram. It was determined that the most significant defects accounted for over 80% of the total, specifically 1) Tombstone defects with a proportion of 52%, and 2) Solder Open defects with a proportion of 29%. The measurement system was analyzed based on the acceptance criteria of the Case Study Company. Brainstorming sessions were conducted with personnel involved in production to create a fishbone diagram for analyzing defects and their impacts. This resulted in Risk Priority Number (RPN) scores above 100 for both Tombstone and Solder Open defects. The possible causes for both defects were identified as follows: 1) soaking time of the solder paste before reflow soldering, 2) spacing between the solder pads on both sides, and 3) solder height. These three factors were then used to design 2^k full factorial experiment at two levels, and the response data was analyzed using Freeman and Tukey's method until suitable conditions were obtained for implementation in actual production. The determined conditions were soaking time of the solder paste before reflow soldering of 30 +/- 0.3 seconds, a spacing of 4.5 millimeters between the solder pads on both sides, and a solder height of 5.0 mils. Experimental results confirmed that the defect rate for Tombstone and Solder Open defects decreased from 8.62% to 0.93%, which was statistically significant when applying the proposed process improvement recommendations. To maintain the improved condition and prevent recurring defects, work standards were established. Additionally, a statistical process control system was developed by using the p-chart. |
URI: | http://cmuir.cmu.ac.th/jspui/handle/6653943832/78469 |
Appears in Collections: | ENG: Independent Study (IS) |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
620632047 - ยุทธนา คำพูน.pdf | การลดข้อบกพร่องในการประกอบแผงวงจรพิมพ์โดยเทคนิคซิกซ์ซิกมา | 22.02 MB | Adobe PDF | View/Open Request a copy |
Items in CMUIR are protected by copyright, with all rights reserved, unless otherwise indicated.