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dc.contributor.authorKento Ogiwaraen_US
dc.contributor.authorKohji Higuchien_US
dc.contributor.authorTomoaki Satoen_US
dc.contributor.authorSuttichai Premrudeepreechacharnen_US
dc.contributor.authorKamon Jirasereeamornkulen_US
dc.description.abstract© 2017 IEEE. In late years, depending on a demand of loads such as FPGA etc., it has been demanded that the output voltage of the DC-DC buck converter is made to decrease and the output current is made to increase. Therefore, it becomes difficult to suppress the dynamic load regulation small. In this paper, it is shown that dynamic load regulation of an interleaved low voltage (1.0[V]) DC-DC buck converter can be suppressed small (5 % of the output voltage, the slew rate 0.6 A/s by an Approximate 2- Degree-of-Freedom (A2DOF) digital control. The controller is implemented by a MD6602 micro controller and it is shown from experiments that the dynamic load regulation is suppressed small enough.en_US
dc.titleApproximate 2-Degree-of-freedom digital control of an interleaved low voltage DC-DC buck converteren_US
dc.typeConference Proceedingen_US
article.title.sourcetitle2017 International Electrical Engineering Congress, iEECON 2017en_US of Electro-Communicationsen_US Universityen_US Mai Universityen_US Mongkuts University of Technology Thonburien_US
Appears in Collections:CMUL: Journal Articles

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