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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Supanut Charoensuksirikul | en_US |
dc.contributor.author | Yuttana Kumsuwan | en_US |
dc.date.accessioned | 2018-12-14T03:54:43Z | - |
dc.date.available | 2018-12-14T03:54:43Z | - |
dc.date.issued | 2018-10-22 | en_US |
dc.identifier.other | 2-s2.0-85057299301 | en_US |
dc.identifier.other | 10.23919/IPEC.2018.8507696 | en_US |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85057299301&origin=inward | en_US |
dc.identifier.uri | http://cmuir.cmu.ac.th/jspui/handle/6653943832/62967 | - |
dc.description.abstract | © 2018 IEEJ Industry Application Society. This paper presents a novel discontinuous space vector modulation (DSVM) technique to reduce the power switching loss by arranging the switching pattern of each an inverter leg for a three-leg voltage source inverter (VSI) fed balanced/unbalanced two-phase loads. This DSVM method provides a typical dwell time calculation as well as the four types of the discontinuous switching sequence selections, which results in optimization switching loss and significantly shares more balanced power, and thermal distributions of each an inverter leg. Especially, in the middle inverter leg, the proposed strategy can mitigate the switching loss up to 1/2 when compared with the conventional continuous SVM (CSVM) method. Calculation and simulation results are shown to verify the effectiveness of the proposed technique. | en_US |
dc.subject | Energy | en_US |
dc.subject | Engineering | en_US |
dc.title | Discontinuous SVM Technique for Three-Leg VSI Fed Balanced/Unbalanced Two-Phase Loads | en_US |
dc.type | Conference Proceeding | en_US |
article.title.sourcetitle | 2018 International Power Electronics Conference, IPEC-Niigata - ECCE Asia 2018 | en_US |
article.stream.affiliations | Chiang Mai University | en_US |
Appears in Collections: | CMUL: Journal Articles |
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